Cell based integrated circuit technology and cell architecture for such circuits have been developed as quick-turns integrated circuit (IC) design methodologies in which pre-designed circuit units or cells are wired together to rapidly implement a new IC functionality. The pre-designed circuit elements are called macro cells which are made by interconnecting unit cells.
A conventional unit cell includes a P-type active region (PMOS transistor) and an N-type active region (NMOS transistor), which are arranged in a first direction. A pair of poly-silicon regions is formed on each of the P-type and N-type active regions. Those poly-silicon regions are extending in parallel to each other in the first direction. The unit cell also includes first and second substrate contact regions, which are arranged in parallel to the P-type active region and N-type active region respectively.
When a circuit, such as a macrolibrary, is made, the poly-silicon regions on the P-type active region are connected to the poly-silicon regions on the N-type active region with conductive lines.
According to the conventional unit cell, power line (Vdd) and ground line (Vss) across the P-type active region and N-type active region; therefore the arrangement of conductive lines becomes complicated. To prevent intersection between signal lines and power line/ground line, the signal lines should be formed on a different layer from the power line and ground line. As a result, it becomes difficult to increase the degree of integration of the IC.
Further, conductive lines connecting the poly-silicon lines on the P-type active region and N-type active regions may across the signal lines, therefore the arrangement of conductive lines becomes complicated. To prevent intersection between such conductive lines and the signal lines, the signal lines should be formed on a different layer. As a result, it becomes difficult to increase the degree of integration of the IC.